A Hdl & Verilog Code: Simulated Output - Manjunatha S. - 書籍 - LAP LAMBERT Academic Publishing - 9783848423248 - 2012年3月21日
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A Hdl & Verilog Code: Simulated Output

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発送予定日 年7月13日 - 年7月23日
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In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between hierarchies of blocks are properly classified as netlist languages used on electric computer-aided design (CAD).

メディア 書籍     Paperback Book   (ソフトカバーで背表紙を接着した本)
リリース済み 2012年3月21日
ISBN13 9783848423248
出版社 LAP LAMBERT Academic Publishing
ページ数 132
寸法 150 × 8 × 226 mm   ·   215 g
言語 ドイツ語