Kishor Sarawadekar

Vlsi Architecture of Block Coder in Jpeg 2000: Understanding Embedded Block Coding Technique of Jpeg 2000: the Vlsi Perspective Kishor Sarawadekar

With the growth in multimedia technology, demand for high speed real time image compression system has also increased. JPEG 2000 still image compression standard is developed to cater such application requirements. It offers numerous advantages over traditional JPEG standard. The key algorithms adopted in this standard are discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). Both the algorithms are computation intensive and when implemented on general purpose processor, they are unsuitable for real time applications. Therefore, to meet the timing constraints imposed by the real time systems dedicated VLSI implementation of these algorithms is imperative. EBCOT is a two-tier coder. Tier-1 is a context based adaptive arithmetic coder and Tier-2 performs layered bit stream formation. Tier-1 is further partitioned into block coder and MQ coder. To a novice, it is difficult to grasp the operating principle of the block coder and hence it is difficult to realize high speed JPEG 2000 architecture. The author has made an attempt to demystify these concepts and presented a simplified VLSI architecture of the block coder in this book.