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System Level Modeling of Phase Locked Loops: Behavioral Analysis and Parameterization Toivo Paavle
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System Level Modeling of Phase Locked Loops: Behavioral Analysis and Parameterization
Toivo Paavle
This work bases on the PhD thesis, defended by the author at Tallinn University of Technology in 2003. The work summarizes the main results of author¿s scientific work in the field of modeling and simulation of phase locked loops (PLLs). The book explains the modeling principles and presents the solutions of problems, for which the designed computer models and simulators were used. As a result, a set of parameters for adequate behavior of the PLL in respective applications is proposed. The scope of modeling and simulation is limited by the analog (classical) and mixed analog/digital structures of the PLL, while two methods for system level modeling (phase-domain and signal-domain modeling) are treated. Dealing with different PLL topics makes the book somewhat eclectic, but helps to apprehend and recognize the benefits of using simple and fast running models as an alternative to expensive commercial software tools for behavioral simulation of PLLs. It might encourage the researches, engineers and students to use cheap general-purpose software for developing self-made models for the study of dynamics and exactness of performance as PLLs as well as other nonlinear dynamic systems.
| メディア | 書籍 Paperback Book (ソフトカバーで背表紙を接着した本) |
| リリース済み | 2009年6月9日 |
| ISBN13 | 9783838302607 |
| 出版社 | LAP Lambert Academic Publishing |
| ページ数 | 100 |
| 寸法 | 225 × 6 × 150 mm · 173 g |
| 言語 | ドイツ語 |