Hardware-in-the-loop Simulation: a Scalable, Component-based, Time-triggered Hardware-in-the-loop Simulation Framework - Martin Schlager - 書籍 - VDM Verlag Dr. Müller - 9783836462167 - 2008年4月21日
カバー画像とタイトルが一致しない場合、正しいのはタイトルです

Hardware-in-the-loop Simulation: a Scalable, Component-based, Time-triggered Hardware-in-the-loop Simulation Framework

価格
¥ 10.634
税抜

遠隔倉庫からの取り寄せ

発送予定日 年5月28日 - 年6月15日
iMusicのウィッシュリストに追加

Safety-critical real-time systems must guarantee correct operation in all operational conditions - even if these conditions are very unlikely to occur (rare events). Hardware-in-the-Loop (HiL) simulation is a common validation technique of real-time systems. In an HiL simulation the environment of a System-Under-Test (SUT) is simulated by an assigned HiL simulator. Thereby, the SUT interacts with the HiL simulator in real-time which necessitates a model of time and interfaces of the HiL simulator that are identical to the model of time and the interfaces of the SUT. In this book an HiL simulation framework is proposed that allows predictable interaction of a distributed HiL simulator and an SUT. This HiL simulation framework comprises configurable simulation components which are interconnected via a time-triggered interaction mechanism. Information flow between the HiL simulator and the SUT is strictly controlled by the progression of synchronized global time and bound to a priori known latency and jitter. This book addresses researchers and engineers in safety-critical domains such as the avionics or automotive industries.

メディア 書籍     Paperback Book   (ソフトカバーで背表紙を接着した本)
リリース済み 2008年4月21日
ISBN13 9783836462167
出版社 VDM Verlag Dr. Müller
ページ数 156
寸法 150 × 220 × 10 mm   ·   213 g
言語 英語