Md. Shabiul Islam

A Novel Rom Design for High Speed Direct Digital Frequency Synthesizer Md. Shabiul Islam

Novel phase accumulator design based on fast adder families such as a modified Brent?Kung adder, carry look-ahead adder and kogge-Stone adder, combined with the pipelining technique to achieve high-frequency resolution and high-speed throughput have been explored and implemented. In 32-bit DDFS system, quarter wave symmetry technique is used to store only one quarter of the sine wave, whereas the ROM look-up table is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits with 534.2:1 compressed ratio.