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Hierarchical Modeling for VLSI Circuit Testing - The Springer International Series in Engineering and Computer Science Debashis Bhattacharya 1990 edition
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Hierarchical Modeling for VLSI Circuit Testing - The Springer International Series in Engineering and Computer Science
Debashis Bhattacharya
To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel.
160 pages, biography
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