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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them Stuart Sutherland 2007 edition
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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
Stuart Sutherland
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.
218 pages, 1 black & white tables, biography
| メディア | 書籍 Hardcover Book (ハードカバー付きの本) |
| リリース済み | 2007年6月26日 |
| ISBN13 | 9780387717142 |
| 出版社 | Springer-Verlag New York Inc. |
| ページ数 | 218 |
| 寸法 | 241 × 164 × 22 mm · 524 g |
| 言語 | 英語 |
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